Triggering MultiStage EG, Version 0.3

Module inputs
* Gate In

Module Output
* Envelope CV Out

Stage Inputs
  * Trigger In (normally from previous stage)
  * 3 position switch  
    RAMP (voltage goes from "EG In" to "FVL" )
    Timed Sustain (trigger out based on Time Delay)
    Infinite Sustain (Voltage Out comes from Final Voltage Level)
  * Time Delay Slider Time is proportional to voltage
  * Final Voltage Level Ending voltage for this stage (FVL)
  * EG Input Starting voltage for this stage

Stage Outputs
  Trigger Out (to next stage)
  EG Out Should match FVL

Each stage is activated indirectly by a "Trigger In" and deactivated (or reset) by a reset from a "Stage Controller". This "Stage Controller" acts as a traffic cop, granting control to the earliest requesting stage (using a 4532 priority encoder). So if all stages sent a Trigger In to the Stage Controller, stage 1 would be activated. The Stage Controller sends an activation trigger that toggles an A/B switch that feeds the "EG Out" from the current stage's voltage control circuitry. When the stage is NOT active, the switch routes "EG In" to "EG Out"

Description of each switch mode

Ramp:
The [Trigger In] for the stage causes the RAMP to select a charging direction, and start charging up or down. The charging "goal" is the FVL.

Finite Sustain:
The [Trigger In] for each stage causes a timer to start running and the output EG comes from the FVL slider.

Infinite Sustain:
The [Trigger In] switches the output EG to the Sustain voltage (FVL), and when the Gate is released, a trigger out signals that the next stage can start. This comes from a Gate-to-trigger converter.

A trigger on a particular stage (through the Stage Controller) resets all of the switches to later stages, thus allowing that stage to control the EG.

I really haven't thought out the fine-grained details. Perhaps a 4532 priority encoder and a 4051 switch to select the EG to use when a trigger occurs (in case of contention, it would use the earliest stage). This would be a part of the "Stage Controller." Just to clarify things, there would be 8 stages sharing a single Stage Controller. Well, here is an initial Block Diagram.

EG Block Diagram


Addendum

For the following discussion, use these abbreviations:

Module Gate IN = GI
Stage Trigger IN = TrigIn
Mode Switch = SW ( RAMP, Timed Sustain, or Infinite Sustain)
Time Delay Slider = TimeDly
Final Voltage Level = FVL
Stage Trigger OUT = TrigOut
Module Envelope Out = EG_OUT

*** Selecting the EG source ***

Gate Input: A "Gate On" goes to a Gate-To-Trigger converter that triggers first stage,
and a "Gate Off" sends a signal to kill the timer in any sustain stage.

When stage one triggers, stages 2 through 8 are "reset." This means later stages act as
Pass-Throughs for the EG_OUT, having no effect on the final voltage. It is strictly
controlled by the current stage. Triggering a stage out of order is not a problem. That
stage "takes control" of the EG_OUT, and resets all subsequent (following) stages.
Since there can be only one active stage, I suggested that the trigger in go to a priority
encoder (CMOS 4532) which picks the first stage that wants to take control.

Stage 3 receives a Trigger IN
Stage 3 requests to take control
A common circuit does several things:
samples the current EG level,
sets (enable) Stage 3's EG switch, and
resets (disables) all other stages.
Stage 3 starts Ramping from the sampled CV (last EG value)
to Final Voltage Level as soon as it is set


*** Timing the Stage ***

Unless the mode switch (SW) is in the infinite sustain position, the trigger in (TI)
goes to a 555 timer circuit that counts down and sends a trigger out when it finishes.
In infinite sustain mode, a common Gate-to-trigger circuit sends a trigger out when
a Gate Off event occurs.

*** EG Control for the Stage ***

If the stage's mode switch is in either sustain position, Feed the EG_OUT from FVL.
Otherwise for RAMP mode, charge up or down perhaps using a voltage controlled
portamento.

It seems that alot of this circuitry could be shared by all stages, with each stage having
a few logic chips to manage which sliders were used to set levels, etc.

For EG control, it really doesn't matter whether Infinite Sustain or Timed Sustain is
selected. In either case, the voltage is taken from the Final Voltage Level slider.


[The next section is an earlier description of this general idea]
ADSR with triggers between stages

The Wierd EG (envelope generator) has a trigger-out that fires after each of the Attack, Decay, Sustain and Release stages ends. This allows chained modulators to start as different stages kick in.

A Modular EG
The MKS-50 Envelope has both time and level adjustments, allowing for either attack and decay, depending on the level of the previous stage. Of course, the "standard" EG has the ADSR stages, but unless you are trying to make a piano or organ patch, other stages might be useful. I'm considering a re-triggerable AD or S module which could be chained to form any required envelope.

Multi-stage EG
Consider the following interface:
Gate In
Trigger In
EG stage type switch (slope or sustain)
Starting Level CV Input (normalled to an adjustment potentiometer)
Ending Level CV Input (normalled to an adjustment potentiometer)
Time CV Input (normalled to an adjustment potentiometer)

Gate Out
Trigger Out
Level Out (pass through of Ending Level CV)

The "Trigger In" jack allows retriggering of a stage. The "Level In" jack is a switching jack, normalled to ground, in any but the first stage, this allows the previous module to pass on the current gate level. The EG stage type switch selects between slope (for Attack or Decay) and sustain. The sustain stage ends when the Gate In goes low. The "Trigger Out" jack signals the end of the current stage.

This unit could be built as a 2U or 3U module with 8 stages, with all out/in values normalled to the next stage (except for those noted as normalled to a pot). This would give, for example, an ADAADDSR. I still need to think about the musical application of this module, with an eye to usability and cost.


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Last modified: Thursday, August 28, 1997